Capa do livro de Source Level Debugging of Verilog Designs
Título do livro:

Source Level Debugging of Verilog Designs

Automated Source Level Debugging of HDL Designs

VDM Verlag Dr. Müller (2010-06-09 )

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ISBN- 1 3:

978-3-639-26287-2

ISBN- 1 0:
3639262875
EAN:
9783639262872
Idioma do livro:
Alemão
Anotações e citações/ texto breve:
Debugging is a very crucial part of hardware design cycle. Once a design is completed, all the possible faults need to be located and corrected. Although the complexity of hardware design is ever increasing, debugging is still mostly performed manually. Today, debugging has become a very painstaking and time consuming task. Model-based diagnosis provides a solid foundation for automated debugging and fault localization but sometimes the quality of the results is questionable as too many diagnosis candidates are reported. The work presented in this book shows how to apply model-based diagnosis to debugging of synthesizable Verilog designs. Moreover, Two extensions of the model based debugging theory to improve the debugging process in terms of reduction in the number of diagnosis candidates reported, are proposed.
Editora:
VDM Verlag Dr. Müller
Website:
http://www.vdm-verlag.de
Por (autor):
Naveed Riaz
Número de páginas:
124
Publicado em:
2010-06-09
Stock:
Disponível
Categoria:
Geral, enciclopédias
Preço:
59 €
Palavras chave:
Model Based Diagnosis, Verilog, Source Level Debugging, Multiple Test Cases, Ackermann constraints

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