Capa do livro de Implementation of a Binary Floating Point Fused Multiply-Add Unit
Título do livro:

Implementation of a Binary Floating Point Fused Multiply-Add Unit

LAP LAMBERT Academic Publishing (2012-12-16 )

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ISBN- 1 3:

978-3-8465-4621-5

ISBN- 1 0:
3846546216
EAN:
9783846546215
Idioma do livro:
Inglês
Anotações e citações/ texto breve:
The fused multiply add (FMA) operation is very important in many scientific and engineering applications. It is a key feature of the floating-point unit (FPU), which greatly increases the floating-point performance and accuracy.Many approaches are developed on floating-point fused multiply add unit to decrease its latency.two of these approaches are implemented in the Verilog hardware description language. ModelSim10.0c is a used to compile Verilog codes and to simulate them.
Editora:
LAP LAMBERT Academic Publishing
Website:
https://www.lap-publishing.com/
Por (autor):
Walaa Abdel Aziz Ibrahim, Hossam Aly Fahmy, Ahmed Hussien Khalil
Número de páginas:
104
Publicado em:
2012-12-16
Stock:
Disponível
Categoria:
Eletrônicas, eletro-tecnologia, tecnologia da comunicação
Preço:
49.00 €
Palavras chave:
Floating Point, Adder, Multiplier, computer arithematic

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