Couverture de Source-Level Debugging of VHDL Designs
Titre du livre:

Source-Level Debugging of VHDL Designs

Models, Methods and Tools

VDM Verlag Dr. MŸller Aktiengesellschaft & Co. KG (23-07-2008 )

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As design density and complexity of digital systems increase, the costs due to design faults increase exponentially. Therefore, detecting, localizing, and correcting faults are crucial issues in today`s fast-paced and fault-prone development process. Test case generation and verification tools detect faults and provide the user with a failing run. Even with a detailed failing run in hand, locating and correcting a fault is a bland and time-consuming chore. Debugging, which is the process of locating and correcting a fault, is not done solely by designers. The verification engineers, the ones who write and run the verification tests, usually spend quite a lot of their own time analyzing the failure traces themselves. Debugging is one of the most time consuming tasks in the effort to improve system quality. It takes 50 to 80 percent of the time used for verification depending on the level of automation of the verification tools. Fault localization may significantly reduce design cycle time by reducing the overall debugging time. This book focuses on models, methods, and techniques for the design and development of debugging tools and specifically addresses verification engineers.
Maison d'édition:
VDM Verlag Dr. MŸller Aktiengesellschaft & Co. KG
de (auteur) :
Bernhard Peischl
Numéro de pages:
Publié le:
Informatique, IT
546.93 HK$
Test, debugging, fault localization, debugging tool, modeling, discrete modeling, VHDL, Verilog, HDL, hardware description language, Model-based Development, model-based reasoning

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