Portada del libro de Design and Modeling of PLL Based CDR for Inter Chip Communications
Título del libro:

Design and Modeling of PLL Based CDR for Inter Chip Communications

Design and Verilog-A Modeling of Phase-Locked Loop Based Clock and Data Recovery Integrated Circuit for 10 Gb/s Intra/Inter Chip Communications in SoC

VDM Verlag Dr. Müller (2009-10-09 )

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ISBN-13:

978-3-639-18554-6

ISBN-10:
3639185544
EAN:
9783639185546
Idioma del libro:
Inglés
Notas y citas / Texto breve:
This work describes the design and implementation of a fully monolithic 10 Gb/s phase and frequency-locked loop based clock and data recovery (PFLL-CDR) integrated circuit, as well as the Verilog-A modeling of an asynchronous serial link based chip to chip communication system incorporating the proposed concept. The frequency-locked loop (FLL) operates independently from the phase-locked loop (PLL), and has a highly-desired feature that once the proper frequency has been acquired, the FLL is automatically disabled and the PLL will take over to adjust the clock edges approximately in the middle of the incoming data bits for proper sampling. Another important feature of the proposed quarter-rate concept is the inherent 1-to-4 demultiplexing of the input serial data stream. In order to verify the accuracy of the proposed quarter-rate concept, a clockless asynchronous serial link incorporating the proposed concept and communicating two chips at 10 Gb/s has been modeled at gate level using the Verilog-A language and time-domain simulated.
Editorial:
VDM Verlag Dr. Müller
Sitio web:
http://www.vdm-verlag.de
Por (autor):
Maher Assaad
Número de páginas:
148
Publicado en:
2009-10-09
Stock:
Disponible
Categoría:
Electrónica, electrotécnica, la tecnología de las comunicaciones
Precio:
59.00 €
Palabras clave:
Phase-Locked Loop, Clock and Data Recovery, Early-Late Phase Detector, Digital Quadricorrelator Frequency Detector, Digital Quadricorrelator Frequency Detector

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