A HDL & Verilog Code的封面
书籍主题:

A HDL & Verilog Code

Simulated Output

LAP LAMBERT Academic Publishing (2012-03-21 )

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ISBN-13:

978-3-8484-2324-8

ISBN-10:
3848423243
EAN:
9783848423248
书籍语言:
英文
作品简介:
In electronics, a hardware description language or HDL is any language from a class of computer languages, specification languages, or modeling languages for formal description and design of electronic circuits, and most-commonly, digital logic. It can describe the circuit's operation, its design and organization, and tests to verify its operation by means of simulation. HDLs are standard text-based expressions of the spatial and temporal structure and behaviour of electronic systems. Like concurrent programming languages, HDL syntax and semantics includes explicit notations for expressing concurrency. However, in contrast to most software programming languages, HDLs also include an explicit notion of time, which is a primary attribute of hardware. Languages whose only characteristic is to express circuit connectivity between hierarchies of blocks are properly classified as netlist languages used on electric computer-aided design (CAD).
出版社 :
LAP LAMBERT Academic Publishing
网址:
https://www.lap-publishing.com/
由(作者):
Manu Sudhan, Manjunatha S.
页码 :
132
发表日期:
2012-03-21
现货:
备有现货
类别:
电子学,电子-技术,通信技术
价格:
59.00 €
关键词:
Architecture, Module, Entity, HDL & VERILOG CODE

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